1. Field of the Invention
The present invention generally relates to level shifters.
2. Description of Related Art
A logic signal is a signal of either a high level or a low level, representing logic 1 or logic 0, respectively. Usually, the low level that represents the logic 0 is taken from a ground node and thus is said to be 0V; the high level that represents the logic 1 is taken from a power supply node. A level shifter receives an input logic signal having a first high level and outputs an output logic signal having a second high level, while both the input logic signal and the output logic signal have the same low level of 0V. If the second high level is higher than the first high level (e.g., the input logic signal is of either 1V or 0V, representing logic 1 and 0, respectively, while the output logic signal is of either 3.3V or 0V, representing logic 1 and 0, respectively), it is referred to as a low-to-high level shifter (L2H); if the second high level is lower than the first high level (e.g., the input logic signal is of either 3.3V or 0V, representing logic 1 and 0, respectively, while the output logic signal is of either 1V or 0V, representing logic 1 and 0, respectively), it is referred to as a high-to-low level shifter (H2L).
As depicted in FIG. 1A, a prior art L2H 100 receives an input logic signal VI+ and its logic complement VI− and outputting an output logic signal VO+ and its logic complement VO−; L2H 100 comprises: a pair of thin-oxide NMOS (short for n-channel metal oxide semiconductor) transistor 101 and 102 for inversion purposes; a pair of thick-oxide NMOS transistors 103 and 104 for cascode purposes; and a pair of thick-oxide PMOS (short for p-channel metal oxide semiconductor) transistor 105 and 106 for latching purposes. Throughout this disclosure, VDDH denotes a supply voltage for a logic signal of a higher high level; while VDDL denotes a supply voltage for a logic signal of a lower high level.
In addition, VB denotes a bias voltage for a cascode device. As known to those of ordinary skill in the art, a thin-oxide device is suitable for handling a logic signal of a low level, while a thick-oxide device is suitable for handling a logic signal of a high level. The structure and operation of L2H 100 is well understood to those of ordinary skill in the art and thus is not described in detail here. An exemplary timing waveform 150 for L2H 100 is depicted in FIG. 1B. As shown in FIG. 1B, VI+ and VI− are complementary and are either VDDL or 0V; to be specific, a rising edge of VI− always accompanies a falling edge of VI+ (e.g., 152 accompanies 151), and a falling edge of VI− always accompanies a rising edge of VI+ (e.g., 156 accompanies 155). On the other hand, VO+ and VO− are either VDDH or 0V, but are not symmetrical, due to the fact that a low-to-high transition takes longer than a high-to-low transition. To be specific, a rising edge of VO•always trails a falling edge of VI+ (e.g., 154 trails 153), and a rising edge of VO+ always trails a falling edge of VI− (e.g., 157 trails 158). This is because a high-to-low transition of VO+ (VO−) is carried out through the inverting NMOS transistor 102 (101) and the cascode NMOS 104 (103), while a low-to-high transition of VO− (VO+) is executed through the inverting NMOS transistor 102 (101), the cascode NMOS transistor 104 (103), and the latching PMOS transistor 105 (106) and thus takes a longer time.
As depicted in FIG. 2A, a prior art H2L 200 receives an input logic signal VI+ and its logic complement VI− and outputs an output logic signal VO+ and its logic complement VO−. The H2L 200 comprises: a pair of thick-oxide NMOS transistors 201 and 202 is provided for inversion purposes; and a pair of thin-oxide PMOS transistors 205 and 206 is provided for latching purposes. H2L 200 is well understood to those of ordinary skill in the art and thus not described in detail here.
An exemplary timing waveform 250 for H2L 200 is depicted in FIG. 2B. As shown in FIG. 2B, VI+ and VI are complementary and are either VDDH or 0V; to be specific, a rising edge of VI− always accompanies a falling edge of VI+ (e.g., 254 accompanies 253), and a falling edge of VI− always accompanies a rising edge of VI+ (e.g., 258 accompanies 257). On the other hand, VO+ and VO− are either VDDR or 0V, but are not symmetrical, due to the fact that a low-to-high transition takes longer than a high-to-low transition. To be specific, a rising edge of VO− always trails a falling edge of VO+ (e.g., 252 trails 251), and a rising edge of VO+ always trails a falling edge of VO− (e.g., 255 trails 256). This is because, a high-to-low transition of VO+ (VO−) is carried through the inverting NMOS transistor 202 (201), while a low-to-high transition of VO− (VO+) is executed through the inverting NMOS transistor 202 (201), and the latching PMOS transistor 205 (206).
In summary, for both L2H 100 of FIG. 1A and H2L 200 of FIG. 2A, the output logic signal is asymmetrical in nature due to the fact that a low-to-high transition takes a longer time than a high-to-low transition. The fundamental reason is that a high-to-low transition can only be fulfilled by NMOS transistor, while a low-to-high transition can only be fulfilled by PMOS transistor; in other words, NMOS transistor establishes the low level (which is 0V, the same for both the input and the output), and PMOS transistor establishes the high level (which is either VDDH or VDDR). In a level shifter (such as L2H 100 of FIG. 1A and H2L 200 of FIG. 2A), NMOS transistor is used for inversion purposes, while PMOS transistor is used for latching purposes; it inherently favors a high-to-low transition. This distorts a duty ratio of the output logic signal.
It is highly desirable that an output of a level shifter is symmetrical between low-to-high and high-to-low transitions.